1. Field of Invention
Exemplary embodiments of the present invention relate to a semiconductor device and a method of manufacturing the same and, more particularly, to a three-dimensional non-volatile memory device having floating gates and a method of manufacturing the same.
2. Description of Related Art
A non-volatile memory device retains data stored therein even in the absence of power supply. Two-dimensional memory devices being manufactured as a single layer on a silicon substrate are reaching physical limits in increasing the degree of integration. Accordingly, three-dimensional non-volatile memory devices that have a plurality of memory cells stacked in a vertical direction on a silicon substrate have been proposed.
FIG. 1 is a cross-sectional view illustrating a cell structure of a conventional three-dimensional non-volatile memory device.
As shown in FIG. 1, a memory device includes a lower select transistor LST, a plurality of memory cells MC, and an upper select transistor UST that are stacked along channel layers 17 that protrude from a substrate 10 having a source region 11 formed thereon.
Each of the memory cells MC includes the channel layer 17, a floating gate 14 having an annular shape to cover the channel layer 17, a tunnel insulating layer 16 interposed between the channel layer 17 and the floating gate 14, control gates 12 stacked alternately with the floating gate 14, and a charge blocking layer 15 interposed between the floating gate 14 and the control gates 12.
According to the cell structure of the conventional memory device, each of the memory cells MC includes one floating gate 14 and two control gates 12. Therefore, each memory cell MC is controlled by two control gates 12, and adjacent memory cells MC in a stacking direction share the control gates 12.
A process of manufacturing the conventional memory device will now be described in brief.
First, conductive layers 12 and interlayer insulating layers 13 are alternately stacked on the substrate 10 having the source region 11 formed thereon. Subsequently, the conductive layers 12 and the interlayer insulating layers 13 are etched to form channel holes, and the interlayer insulating layers 13 exposed through the channel holes are partially etched by a given depth to form recessed regions. Next, the charge blocking layers 15 are formed on inner walls of the channel holes having the recessed regions therein, and the floating gates 14 are formed in the recessed regions. The tunnel insulating layers 16 are formed in the channel holes, and channel layers 17 are formed thereon. Finally, the conductive layers 12 and the interlayer insulating layers 13 are etched to form slits between the channel layers 17, and an insulating layer 18 is formed in each of the slits.
According to the above-described process, the thickness of the floating gates 14, i.e., the width of floating gates 14 in FIG. 1, is determined depending on how deep the interlayer insulating layers 13 are etched. However, since it is difficult to etch the interlayer insulating layers 13 evenly, the thickness of the floating gate 14 differs for each memory cell MC. In addition, since the charge blocking layer 15 and the floating gate 14 are formed in the recessed region, the thickness of the interlayer insulating layer 13 is to be increased in order to form the floating gate 14 with a sufficient thickness. However, this results in an increase in thickness of the stacked layers, and the difficulty in the etching process performed to form channel holes is also increased.